1. Field of the Invention
The present invention relates to a floating point multiplier composed of integrated circuits. More specifically, the invention relates to a floating point multiplier which can be easily tested after production.
2. Description of the Related Art
When performing a floating point multiplication, an adding process for exponential parts of a multiplied value and a multiplying value, a multiplying process for a mantissa, a rounding process for the product of multiplication of the mantissa, and a normalizing process are performed to finally obtain the result of the multiplication. In the floating point multiplication, the mantissa of the result is obtained from upper half bits of the product of multiplication of the mantissa of the two inputs and a total sum of truncated lower bits. Concerning such floating point multiplication method have been described in IEEE 754, "IEEE Standard for Binary Floating-Point Arithmetic".
In the conventional floating point multiplier, exponential parts of the floating point multiplied value and multiplying value separated through the preceding process step are added by an exponential part adder. On the other hand, the mantissa of the floating point multiplied value and the multiplying values are multiplied by a binary multiplier. When the mantissa is n bits, multiplication is performed by inputting p bits (p.gtoreq.n) of the mantissa to the binary multiplier. From the binary multiplier, 2p-1 bits of a product of the multiplication are output. From the product of multiplication of the mantissa in the binary multiplier, a sticky bit of the lower m bits is derived.
On the other hand, on the basis of the sticky bit, a rounding process and a normalizing process for the upper q bits (q&gt;n) are performed so that a final product of multiplication can be output by combining the results of the rounding process and the normalizing process with the mantissa processed through the adding process.
The binary multiplier receives two binary values of bit length p (p.gtoreq.n) assuming the length of the mantissa of floating point is n bits, and then outputs two binary values of bit length (2p-1). The output to be input to the rounding process and the normalizing process are the upper q bits and a sticky bit of the truncated lower (2p-1-q=m) bits.
As set forth above, in the conventional floating point multiplier, the lower m bits of the mantissa of the product of the binary multiplication are aggregated as a sticky bit. Therefore, even when there is a faulty gate in the binary multiplier, it is difficult to detect failure of the gate on the basis of the output. Concerning the gate corresponding to the upper bits of the binary multiplier, a test can be performed by monitoring the external output since the upper bits are externally output as the final result of multiplication. Therefore, there should not have been raised the problems as those raised in testing the lower bits.
In order to detect the failure of 1 bit in the lower output in question, it becomes necessary apply a test pattern with such multiplied values and multiplying values to set all other lower output bits to "0" other than the bit in question, and vary the bit in question between "0" and "1". Accordingly, for testing failure of all bits of the lower output, a large number of test patterns set forth above are to be prepared for each digit of the lower bits for performing testing by inputting each test pattern, one by one, thereby making testing very cumbersome. Also, since the sticky bit of an OR gate is an internal signal instead of an externally output signal, testing becomes even more cumbersome.
The following is an example of the test pattern:
Assuming that the lower m bits of the output of the binary multiplier is 5 bits, in order to detect failure of the gate for the second least significant bit, for example, "10101" and "11010" are input as the multiplied value and the multiplying value. When these two values are multiplied, if failure is not caused in the gate of the binary multiplier, the following calculation will be performed: ##EQU1## From this, "1000100010", in which among the lower 5 bits, the second least significant bit in question is "1" and all other bits are "0" is output. If the gate corresponding to the second least significant bit is in failure, the second bit becomes "0" so that the sticky bit of the lower 5 bits becomes "0". Thus, failure of the gate can be detected.
Assuming that the lower m bits of the output of the binary multiplier is 5 bits, in order to detect failure of the gate for the fourth lower bit, for example, "10111" and "11000" are input as the multiplied value and the multiplying value. When these two values are multiplied, if failure is not caused in the gate of the binary multiplier, the following calculation will be performed: ##EQU2## From this, "1000101000", in which among the lower 5 bits, the fourth lower bit in question is "1" and all other bits are "0" is output. If the gate corresponding to the second least significant bit is in failure, the fourth lower bit becomes "0" so that the sticky bit of the lower 5 bits becomes "0". Thus, failure of the gate can be detected.
As set forth above, since failure of the gate is detected from the result of the multiplication of a large number of test patterns which are preliminarily prepared, the testing is very labor and time intensive work.